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dual/quad , low power, high speed jfet operati onal amplifiers data sheet op282 / op482 rev. i document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specif ications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 1991C 2013 analog devices, inc. all rights reserved. technical support www.analog.com f eatures high slew rate: 9 v/s wide bandwidth: 4 mhz low supply current: 250 a/amplifier max imum low offset voltage: 3 mv maximum low bias current: 100 pa maximum fast settling time common - mode range includes v+ unity - gain stable 14- ball wafer level chip scale for quad a pplications active filters fast amplifiers integrators supply current monitoring g eneral description the op282 / o p482 dual and quad operational amplifiers feature excellent speed at exceptionally low supply currents. the slew rate is typically 9 v/s with a supply current of less than 250 a per amplifier. these unity - gain stable amplifiers have a typical gain bandw idth of 4 mhz. the jfet input stage of the op282 / op482 ensures that the bias current is typically a few picoamps and is less tha n 500 pa over t he full temperature range. the o ffset voltage is less than 3 mv for the dual amplifier and less than 4 mv for the quad amplifier . with a wide output swing ( within 1.5 v of each supply ) , low power consumption, and high slew rate, the op282 / op482 are ideal for battery - powered syste ms or power - restricted applica - tions. an input common - mode range that includes the positi ve supply makes the op282 / op482 an excellent choice for high - side signal conditioning. the op282 / op482 are specified over the extended industrial temperature range. the op282 is available in the standard 8 - lead , narrow soic and msop packages. th e op482 is available in the pdip and narrow soic packages , as well as a 14- ball wlcsp. pin connections 1 2 3 4 5 6 7 8 out a ?in a +in a v? op-482 v+ out b ?in b +in b op282 00301-001 figure 1 . 8 - lead , narrow - body soic (s - suffix) [r - 8] 00301-002 out a 1 ?in a 2 +in a 3 v? 4 v+ 8 out b 7 ?in b 6 +in b 5 op282 t o p view (not to scale) figure 2 . 8 - lead msop [rm - 8] 1 2 3 4 5 6 7 14 13 12 1 1 10 9 8 out a ?in a +in a v+ +in b ?in b out b out d ?in d +in d v? +in c ?in c out c op482 ? + + ? ? + + ? 00301-003 figure 3 . 14 - lead pdip (p - suffix) [n - 14] 1 2 3 4 5 6 7 14 13 12 1 1 10 9 8 out a ?in a +in a v+ +in b ?in b out b out d ?in d +in d v? +in c ?in c out c op482 00301-004 figure 4 . 14 - lead , narrow - body soic (s - suffix) [r - 14] t op view (bal l side down) not to scale 00301-048 bal l a1 corner out a +in d v? +in c out c out d ?in a v+ ?in b out b ?in d +in a +in b ?in c a b c d e f 1 2 3 g h j figure 5 . 14 - ball wlcs p [ cb - 14 - 2 ]
op282/op482 data sheet rev. i | page 2 of 16 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 pin connections ............................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical characteristics ............................................................. 3 absolute maximum ratings ............................................................ 4 thermal resistance ...................................................................... 4 esd caution ...................................................................................4 typical performance characteristics ..............................................5 applications information .............................................................. 12 high - side signal conditioning ................................................ 1 2 phase inversion ........................................................................... 12 active filters ............................................................................... 12 programmable state variable filter ......................................... 13 outlin e dimensions ....................................................................... 14 ordering guide .......................................................................... 16 r evision history 9/13 rev. h to rev. i changes to figure 5 .......................................................................... 1 updated outline dimensions ....................................................... 14 changes to ordering guide .......................................................... 16 9/ 10 rev. g to rev. h added wlcsp .................................................................... universal changes to features section ............................................................ 1 changes to general description section ...................................... 1 added figure 5 ; renumbered sequentially .................................. 1 changes to large - signal voltage gain parameter , table 1 ......... 3 changes to table 2 , thermal resistance secti on, and table 3 ... 4 change to figure 30 ......................................................................... 9 added figure 53 .............................................................................. 16 changes to ordering guide .......................................................... 16 7/08 rev. f to rev. g changes to phase inversion section ............................................ 12 deleted figure 45 ............................................................................ 12 added figure 45 and figure 46 ..................................................... 12 updated outline dimensions ....................................................... 14 changes to ordering guid e .......................................................... 16 10/04 rev. e to rev. f deleted 8 - lead pdip ......................................................... universal added 8 - lead msop ......................................................... universal changes to format and layout ......................................... universal changes to features .......................................................................... 1 changes to pin configurations ....................................................... 1 changes to general description .................................................... 1 changes to specifications ................................................................ 3 changes to absol ute maximum ratings ....................................... 4 changes to table 3 ............................................................................ 4 added figure 5 through figure 20; renumbered successive figures .............................................................................. 5 updated figure 21 and figure 22 .................................................... 7 updated figure 23 and figure 27 .................................................... 8 updated figure 29 ............................................................................. 9 updated figure 35 and figure 36 ................................................. 10 updated figure 43 .......................................................................... 11 ch anges to applications information ......................................... 12 changes to figure 44 ...................................................................... 12 deleted op282/op482 spice macro model section .................... 9 deleted figure 4 ................................................................................. 9 deleted op282 spice marco model ............................................. 10 updated outline dimensions ....................................................... 14 changes to ordering guide .......................................................... 14 10/02 rev. d to rev. e edits to 8 - lead epoxy dip (p - suffix) pin ...................................... 1 edits to ordering guide ................................................................... 3 edits to outline dimensions ......................................................... 11 9/02 rev. c to rev. d edits to 14 - lead soic (s - suffix) pin ............................................. 1 replaced 8 - lead soic (s - suffix) ................................................. 11 4/02 rev. b to rev. c wafer test limits deleted ................................................................ 2 edits to absolute max imum ratings .............................................. 3 dice characteristics deleted ............................................................ 3 edits to ordering guide ................................................................... 3 edits to figure 1 ................................................................................. 7 edits to figure 3 ................................................................................. 8 20- position chip carrier (rc suffix) deleted ........................... 11
data sheet op282/op482 rev. i | page 3 of 16 specifications electrical character istics at v s = 15.0 v, t a = 25c, unless otherwise noted; applies to both a and g grade s. table 1. parameter symbol test conditions /comments min typ max unit input characteristics offset voltage v os op282 0.2 3 mv op282 , ? 40 c t a +85 c 4.5 mv op482 0.2 4 mv op482 , ? 40 c t a +85 c 6 mv input bias current i b v cm = 0 v 3 100 pa v cm = 0 v 1 500 pa input offset current i os v cm = 0 v 1 50 pa v cm = 0 v 1 250 pa input voltage range ?11 +15 v common - mode rejection ratio cmrr ? 11 v v cm +15 v, ? 40 c t a +85 c 70 90 db large - signal volt age gain a vo r l = 10 k? , v o = 13.5 v 20 v/mv r l = 10 k?, ? 40 c t a +85 c 15 v/mv offset voltage drift v os / t 10 v/c bias current drift i b / t 8 pa/c output characteristics output voltage high v oh r l = 10 k? 13.5 13.9 v outp ut voltage low v ol r l = 10 k? ?13.9 ?13.5 v short - circuit limit i sc source 3 10 ma sink ?12 ?8 ma open - loop output impedance z out f = 1 mhz 200 ? power supply power supply rejection ratio psrr v s = 4.5 v to 18 v, ? 40 c t a +85 c 25 316 v/v supply current/amplifier i sy v o = 0 v, ?40 c t a 85 c 210 250 a supply voltage range v s 4.5 18 v dynamic performance slew rate sr r l = 10 k? 7 9 v/s full - power bandwidth bw p 1% distortion 125 khz settling time t s to 0.01% 1.6 s gain bandwidth product gbp 4 mhz phase margin ? m 55 degrees noise performance voltage noise e n p -p 0.1 hz to 10 hz 1.3 v p -p voltage noise density e n f = 1 khz 36 nv/hz current noise density i n 0.01 pa/hz 1 the input bias and offset currents are characterized at t a = t j = 85 c. bias and offset currents are guaranteed but not tested at ? 40 c.
op282/op482 data sheet rev. i | page 4 of 16 absolute ma ximum ratings table 2. parameter rating supply voltage 18 v input voltage 18 v differential input voltage 1 36 v output short - circuit duration indefinite storage temperature range ? 65 c to +150 c operating temperature range ? 40 c to +85 c junction temperature range ? 65 c to +150 c lead temperature (soldering 60 sec) 300 c 1 for supply voltages less than 18 v, the absolute maximum input voltage is equal to the supply voltage. stresses above those listed under absolute m aximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to ab solute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst - case conditions, that is, a device in socket for pdip . ja is specified for a device soldered in the circuit board for soic _n , msop , and wlcsp package s. this was measured using a standard 4 - layer board. table 3. package type ja jc unit 8- lead msop [rm] 142 45 c/w 8- lead soic _n ( s - suffix ) [r] 120 45 c/w 14- lead pdip (p - suffix) [n] 83 39 c/w 14- lead soic _n (s - suffix) [r] 112 35 c/w 14- ball wlcsp [ cb ] 1, 2 70 16 c/w 1 simulated thermal numbe rs per jesd51 - 9. 2 junction - to - board thermal resistance. esd caution
data sheet op282/op482 rev. i | page 5 of 16 typical performance characteristics frequenc y (hz) open-loo p gain (db) 1k ?40 ?20 60 80 10k 1m 10m 00301-005 100k 20 40 0 v s = 15v t a = 25 c phase (degrees) ?45 135 45 90 0 ?90 180 figure 6 . op282 open - loop gain and phase vs. fre quency temper a ture (c) open-loo p gain (v/mv) ?75 0 5 35 45 ?25 100 125 00301-006 25 15 25 10 v s = 15v r l = 10k ? 20 30 40 75 50 0 ?50 figure 7 . op282 open - loop gain vs. temperature load ca p aci t ance (pf) overshoot (%) 0 0 10 70 80 200 400 500 00301-007 30 50 20 40 60 300 100 v s = 15v r l = 2k ? v in = 100mv p-p a vcl = 1 t a = 25 c +os ?os figure 8 . op282 small - signal overshoot vs. load capacitance frequenc y (hz) closed-loo p gain (db) 1k ?30 ?20 60 70 10k 1m 10m 00301-008 100k 20 40 0 v s = 15v t a = 25 c ?10 50 10 30 a vcl = 1 00 a vcl = 1 0 a vcl = 1 figure 9 . op282 closed - loop gain vs. frequency temper a ture ( c) slew r a te (v/ s) ?75 0 5 30 ?25 100 125 00301-009 25 15 25 10 v s = 15v r l = 10k ? c l = 50pf 20 75 50 0 ?50 ?sr +sr figure 10 . op282 slew rate vs. temperature temper a ture ( c) input bias current (pa) ?75 0.1 1000 ?25 100 125 00301-010 25 1 100 10 75 50 0 ?50 v s = 15v v cm = 0v figure 11 . op282 input bias current vs. temperature
op282/op482 data sheet rev. i | page 6 of 16 frequenc y (hz) vo lt age noise densit y (nv/ hz) 10 1 1000 100 10k 00301-0 1 1 1k 100 10 v s = 15v t a = 25 c figure 12 . op282 voltage noise density vs. frequency common-mode vo lt age (v) input bias current (pa) ?15 0.1 1000 10 15 00301-012 ?5 1 100 10 5 0 ?10 v s = 15v t a = 25 c figure 13 . op282 input bias current vs. common - mode volta ge supp l y vo lt age (v) supp l y current ( a) 0 450 480 20 00301-013 10 455 465 460 15 5 t a = 25 c 470 475 figure 14 . op282 supply current vs. supply voltage supp l y vo lt age (v) output vo lt age swing (v) 0 ?20 20 20 00301-014 10 ?15 ?5 ?10 15 5 t a = 25 c r l = 10k ? 0 15 v oh v o l 5 10 figure 15 . op2 82 output voltage swing vs. supply voltage frequenc y (hz) output impedance ( ? ) 1k 0.1 100 1000 10k 1m 100 00301-015 100k 1 10 v s = 15v t a = 25 c a vcl = 100 a vcl = 10 a vcl = 1 figure 16 . op282 closed - loop output impedance vs. frequency temper a ture ( c) supp l y current ( a) ?50 450 480 125 00301-016 25 455 75 0 460 475 465 470 ?25 50 100 figure 17 . op282 supply current vs. temperature
data sheet op282/op482 rev. i | page 7 of 16 load resis t ance ( ? ) absolute output vo lt age (v) 0 6 16 1k 10k 100 00301-017 2 4 v s = 15v t a = 25 c v o l v oh 12 8 10 14 figure 18 . op282 absolute output voltage vs. load resistance frequenc y (hz) psrr (db) 1k ?60 40 140 10k 1m 100 00301-018 100k 0 20 ?40 ?20 60 100 120 80 ?psrr +psrr v s = 15v t a = 25 c figure 19 . op282 psrr vs. frequency temper a ture ( c) shor t -circuit current (ma) ?50 0 14 125 00301-019 25 4 75 0 6 12 8 10 ?25 50 100 2 sink source v s = 15v t a = 25 c figure 20 . op282 short - circuit current vs. temper ature frequenc y (hz) maximum output swing (v p-p) 100 0 5 25 30 1k 100k 1m 00301-020 10k 15 20 10 v s = 15v t a = 25 c r l = 10k ? a vcl = 1 figure 21 . op282 maximum output swing vs. frequency frequenc y (hz) cmrr (db) 1k ?60 40 140 10k 1m 100 00301-021 100k 0 20 ?40 ?20 60 100 120 80 v s = 15v t a = 25 c figure 22 . op282 cmrr vs. frequency v os ( v) units ?2000 0 200 00301-022 ?400 80 ?1200 120 160 40 400 1200 2000 v s = 15v t a = 25 c 300 op282 (600 o p amps) 0 figure 23 . op282 vos distribution , soic _n package
op282/op482 data sheet rev. i | page 8 of 16 tcv os ( v/ c) units 0 0 400 00301-023 20 80 16 120 160 40 28 32 36 24 200 280 320 360 240 4 12 8 v s = 15v 300 op282 (600 o p amps) figure 24 . op282 tcvos distribution , soic _n package frequenc y (hz) 1k 10k 100k 1m 100m 10m 80 open-loo p gain (db) phase (degrees) 90 135 0 45 180 60 40 20 0 v s = 15v t a = 25 c 00301-024 figure 25 . op482 open - loop gain and phase vs. frequency 125 100 50 75 25 0 ?75 ?50 ?25 temper a ture ( c) open-loo p gain (v/mv) 30 35 25 20 15 10 5 v s = 15v r l = 10k ? 00301-025 0 figure 26 . op482 open - loop gain vs. temperature overshoot (%) 500 0 300 100 200 400 70 10 0 60 50 40 30 20 load ca p aci t ance (pf) a vcl = 1 neg a tive edge v s = 15v r l = 2k ? v in = 100mv p-p 00301-026 a vcl = 1 positive edge figure 27 . op482 small - signal overshoot vs. load capacitance frequenc y (hz) 1k 10k 100k 1m 100m 10m 60 closed-loo p gain (db) 40 20 10 0 50 30 ?10 ?20 00301-027 a vcl = 10 a vcl = 1 a vcl = 100 v s = 15v t a = 25 c f igure 28 . op482 closed - loop gain vs. frequency ?sr ?75 temper a ture ( c) ?50 ?25 0 25 50 75 100 125 5 10 25 15 20 +sr slew r a te (v/ s) 00301-028 v s = 15v r l = 10k ? c l = 50pf 0 figure 29 . op482 slew rat e vs. temperature
data sheet op282/op482 rev. i | page 9 of 16 1000 1.0 0.1 100 10 input bias current (pa) temper a ture (c) 125 ?25 ?50 25 0 75 100 00301-029 v s = 15v v cm = 0v ?75 50 figure 30 . op482 input bias current vs. temperature 60 55 phase margin (degrees) ?75 temper a ture ( c) ?50 ?25 0 25 50 75 100 125 v s = 15v r l = 10k ? gbw gain bandwidth product (mhz) 50 45 40 5.0 4.5 4.0 3.5 3.0 00301-030 ? m figure 31 . op482 phase margin and gain bandwidth product vs. temperature frequenc y (hz) 10 100 1k 10k 80 0 20 10 40 30 50 60 70 voltage noise density (nv/ hz) 00301-031 v s = 15v t a = 25 c figure 32 . op482 voltage noise density vs. frequency common-mode vo lt age (v) 15 ?15 0 5 10 ?10 ?5 input bias current (pa) 100 1 1000 0.1 10 00301-032 v s = 15v t a = 25 c figure 33 . op482 input bias current vs. common - mode voltage supp l y vo lt age (v) 15 0 20 10 5 rel a tive supp l y current (i sy ) 1.10 0.90 1.15 0.85 1.00 1.05 0.95 00301-033 t a = 25 c figure 34 . op482 relative supply current v s. supply voltage supp l y vo lt age (v) 15 0 10 5 20 ?5 output vo lt age swing (v) 0 15 5 10 20 ?10 ?20 ?15 00301-034 r l = 10k ? t a = 25 c figure 35 . op482 output voltage swing vs. supply voltage
op282/op482 data sheet rev. i | page 10 of 16 impedance ( ? ) 600 0 300 100 200 500 400 1m 1k 100 100k 10k frequenc y (hz) a vcl = 10 00301-035 v s = 15v t a = 25 c a vcl = 1 a vcl = 100 figure 36 . op482 closed - loop output impedance vs. frequency rel a tive supp l y current (i sy ) temper a ture ( c) 1.20 0.80 0.90 0.85 1.00 0.95 1.05 1.10 1.15 ?50 ?75 125 100 75 50 25 0 ?25 00301-036 v s = 15v figure 37 . op482 relative supply current vs. temperature load resis t ance ( ? ) 10k 1k 100 absolute output vo lt age (v) 16 0 2 8 6 10 12 14 4 positive swing neg a tive swing 00301-037 v s = 15v t a = 25 c figure 38 . op482 maximum output voltage vs. load resistance psrr (db) 100 20 40 0 20 80 60 1m 1k 100 100k 10k frequenc y (hz) +psrr 00301-038 v s = 15v v = 100mv t a = 25 c ?psrr figure 39 . op482 power supply rejection ratio (psrr) vs. frequency shor t -circuit current (ma) 20 15 5 10 sink source temper a ture ( c) 75 ?75 0 25 50 ?50 ?25 100 125 00301-039 v s = 15v 0 figure 40 . op482 short - circuit current vs. temperature maximum output swing (v) 30 0 15 5 10 25 20 100k 10k 1k 1m frequenc y (hz) 00301-040 v s = 15v t a = 25c a vcl = 1 r l = 10k ? figure 41 . op482 maximum output swing vs. frequency
data sheet op282/op482 rev. i | page 11 of 16 cmrr (db) 100 ?20 40 0 20 80 60 1m 1k 100 100k 10k frequenc y (hz) 00301-041 v s = 15v t a = 25 c v cm = 100mv figure 42 . op482 common - mode rejection ratio (cmrr) vs. frequency units 0 600 700 300 100 200 400 500 2000 ?1600 ?2000 1600 1200 800 400 0 ?400 ?800 ?1200 v os ( v) 00301-045 v s = 15v t a = 25 c 300 op482 (1200 o p amps) figure 43 . op482 vos distribution , p dip package units 320 0 80 40 160 120 200 240 280 0 00301-043 32 28 24 12 20 16 8 4 tcv os ( v/ c) figure 44 . op482 tcv os distribution , pdip package
op282/op482 data sheet rev. i | page 12 of 16 applications informa tion the op282 and op482 are dual and quad jfet op amps that are optimized for high speed at low power . this combination makes these amplifiers excellent choices for battery - powered or low power applications that require above average performance. applications benefiting from this performance combination include telecommunications, geophysical exploration, portable medical equipment, and navigational instrumentation. high - side signal conditio ning m any applications require the sensing of signals near the positive rail. op282 and op482 were tested and are guaranteed over a common - mode range (?11 v v cm +15 v) that includes the positive supply. one application where such sensing is commonly used is in the sensing of power supply c urrents. therefore, the op282 / op482 can be used in current sensing applications, such as the partial circuit shown in figure 45. i n this circuit, the voltage drop across a low value resistor, such as the 0.1 ? shown here, is amplified and compared to 7.5 v. the output can then be used for current limiting. 15v 100k ? 500k ? 0.1 ? 500k ? 100k ? r l 1/2 op282 00301-046 figure 45 . high - side signal conditioning phase inve rsion most jfet input amplifiers invert the phase of the input signal if either input exceeds the input common - mode range. for the op282 / op482 , a negative signal in excess of 11 v cause s phase inversion. this is caused by saturation of the input stage , leading to the forward - biasing of a gate - drain diod e. phase reversal in the op282 / op482 can be prevented by using schottky diodes to clamp the input terminals to each other and to the supplies. in the simple buffer circuit shown in figure 46 , d1 protects the op amp against phase reversal. r1, d2 , and d3 limit the input current when the input exceeds the supply rail. the resistor should be selected to limit the amount of input current below the absolute maximum rating. 00301-042 d1 in5711 v+ op282/ op482 v+ v out v in v? v? d2 in5711 r1 10k? d3 in5711 figure 46 . phase reversal solution circuit 00301-044 time (200s/div) volt age (5v/div) 2 v s = 15v v in v out figure 47 . no phase reversal active filters the wide bandwidth and high slew rates of the op282 / op482 make either one an excellent choice for many filter applications. there are many active filter configurations, but the four most popular configurations are butterworth, elliptic , bessel, and ch ebyshev. each type has a response that is optimized for a given characteristic , as shown in table 4 . table 4. active filter configurations type selectivity overshoot phase amplitude (pass band) amplitude (stop band) butterworth moderate good maximum f lat chebyshev good moderate nonlinear equal r ipple elliptic best poor equal r ipple equal r ipple bessel (thompson) poor best linear
data sheet op282/op482 rev. i | page 13 of 16 programmable state variable filter the circuit shown in figure 48 can be used to accurately program the q, the cutoff frequency ( f c ) , and the gain of a two - pole state variable filter. op482 device s have been used in this design be cause of their high bandwidths, low power, and low noise. this circuit takes only three packages to build because of the quad configuration of the op amps and dacs. the dacs shown are used in the voltage mode; therefore, many values are dependent on the ac curacy of the dac only and not on the absolute values of the dacs resistive ladders. this makes this circuit unusually accurate for a programmable filter. adjusting dac 1 changes the signal amplitude across r1; therefore, the dac attenuation times r1 dete rmines the amount of signal current that charges the integrating capacitor, c1. this cutoff frequency can now be expressed as ? ? ? ? ? ? = 256 2 1 d1 r1c1 f c where d1 is the digital code for the dac. the gain of this circuit is set by adjusting d3. the gain equa tion is ? ? ? ? ? ? = 256 d3 r5 r4 gain dac 2 is used to set the q of the circuit. adjusting this dac controls the amount of feedback from the band - pass node to the input summing node. note that the digital value of the dac is in the numerator; therefore, zero co de is not a valid operating point. ? ? ? ? ? ? = d2 r3 r2 q 256 r5 2k ? 1/4 op482 v in 1/4 dac 8408 high p ass c1 1000pf r4 2k ? r6 2k ? r7 2k ? 1/4 op482 r1 2k ? 1/4 op482 1/4 dac 8408 1/4 op482 r1 2k ? 1/4 op482 1/4 dac 8408 1/4 op482 c1 1000pf low p ass 1/4 op482 1/4 op482 1/4 dac 8408 band p ass r2 2k ? r3 2k ? 00301-047 figure 48 . programmable state variable filter
op282/op482 data sheet rev. i | page 14 of 16 outline dimensions compliant to jedec standards mo-187-aa 6 0 0.80 0.55 0.40 4 8 1 5 0.65 bsc 0.40 0.25 1.10 max 3.20 3.00 2.80 coplanarity 0.10 0.23 0.09 3.20 3.00 2.80 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 10-07-2009-b figure 49 . 8 - lead mini small outline package [msop] (rm - 8) dimensions sh own in millimeters c o n t r o l l i n g d i m e n s i o n s a r e i n m i l l i m e t e r s ; i n c h d i m e n s i o n s ( i n p a r e n t h e s e s ) a r e r o u n d e d - o f f m i l l i m e t e r e q u i v a l e n t s f o r r e f e r e n c e o n l y a n d a r e n o t a p p r o p r i a t e f o r u s e i n d e s i g n . c o m p l i a n t t o j e d e c s t a n d a r d s m s - 0 1 2 - a a 0 1 2 4 0 7 - a 0 . 2 5 ( 0 . 0 0 9 8 ) 0 . 1 7 ( 0 . 0 0 6 7 ) 1 . 2 7 ( 0 . 0 5 0 0 ) 0 . 4 0 ( 0 . 0 1 5 7 ) 0 . 5 0 ( 0 . 0 1 9 6 ) 0 . 2 5 ( 0 . 0 0 9 9 ) 4 5 8 0 1 . 7 5 ( 0 . 0 6 8 8 ) 1 . 3 5 ( 0 . 0 5 3 2 ) s e a t i n g p l a n e 0 . 2 5 ( 0 . 0 0 9 8 ) 0 . 1 0 ( 0 . 0 0 4 0 ) 4 1 8 5 5 . 0 0 ( 0 . 1 9 6 8 ) 4 . 8 0 ( 0 . 1 8 9 0 ) 4 . 0 0 ( 0 . 1 5 7 4 ) 3 . 8 0 ( 0 . 1 4 9 7 ) 1 . 2 7 ( 0 . 0 5 0 0 ) b s c 6 . 2 0 ( 0 . 2 4 4 1 ) 5 . 8 0 ( 0 . 2 2 8 4 ) 0 . 5 1 ( 0 . 0 2 0 1 ) 0 . 3 1 ( 0 . 0 1 2 2 ) c o p l a n a r i t y 0 . 1 0 figure 50 . 8 - lead standard small outline package [soic _n ] narrow body s- suffix (r - 8) dimensions shown in millimeters and (inches)
data sheet op282/op482 rev. i | page 15 of 16 compliant t o jedec s t andards ms-001 controlling dimensions are in inches; millimeter dimensions (in p arentheses) are rounded-off inch equi v alents for reference on l y and are not appropri a te for use in design. corner leads m a y be configured as whole or half leads. 070606- a 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.150 (3.81) 0.130 (3.30) 0. 1 10 (2.79) 0.070 (1.78) 0.050 (1.27) 0.045 (1.14) 14 1 7 8 0.100 (2.54) bsc 0.775 (19.69) 0.750 (19.05) 0.735 (18.67) 0.060 (1.52) max 0.430 (10.92) max 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.015 (0.38) gauge plane 0.210 (5.33) max se a ting plane 0.015 (0.38) min 0.005 (0.13) min 0.280 (7. 1 1) 0.250 (6.35) 0.240 (6.10) 0.195 (4.95) 0.130 (3.30) 0. 1 15 (2.92) figure 51 . 14 - lead plastic dual in - line package [pdip] p - suffix (n - 14) dimension shown in inches and (millimeters) controlling dimensions are in millimeters; inch dimensions (in p arentheses) are rounded-off millimeter equi v alents for reference on l y and are not appropri a te for use in design. compliant t o jedec s t andards ms-012-ab 060606- a 14 8 7 1 6.20 (0.2441) 5.80 (0.2283) 4.00 (0.1575) 3.80 (0.1496) 8.75 (0.3445) 8.55 (0.3366) 1.27 (0.0500) bsc sea ting plane 0.25 (0.0098) 0.10 (0.0039) 0.51 (0.0201) 0.31 (0.0122) 1.75 (0.0689) 1.35 (0.0531) 0.50 (0.0197) 0.25 (0.0098) 1.27 (0.0500) 0.40 (0.0157) 0.25 (0.0098) 0.17 (0.0067) coplanarit y 0.10 8 0 45 figure 52 . 14 - lead standard small outline package [soic _n ] narrow body s- suffix (r - 14) dimensions shown in millimeters and (inches)
op282/op482 data sheet rev. i | page 16 of 16 1.165 1.128 1.090 2.160 2.123 2.085 a b c d e f 1 2 3 bot t om view (bal l side up) 1.60 ref 0.694 ref 0.40 bsc 0.20 bsc 0.347 bsc 0.347 bsc g h j 0.287 0.267 0.247 0.415 0.400 0.385 0.230 0.200 0.170 0.645 0.600 0.555 t op view (bal l side down) end view bal l a1 identifier 09- 1 1-2012-b sea ting plane coplanarity 0.05 figure 53 . 14 - ball wafer level chip scale package [wlcsp] cb - 14- 2 controlling dimensions are millimeters ordering guide model 1 temperature range package description package option branding op282armz ? 40 c to +85 c 8- lead msop rm -8 a0b o p282armz - reel ? 40 c to +85 c 8- lead msop rm -8 a0b op282gs ? 40 c to +85 c 8 - lead soic _n s - suffix (r - 8) op282gs - reel ? 40 c to +85 c 8- lead soic _n s - suffix (r -8) op282gs - reel7 ? 40 c to +85 c 8- lead soic _n s - suffix (r -8) op282gsz ? 40 c to +85 c 8- lead s oic _n s - suffix (r -8) op282gsz - reel ? 40 c to +85 c 8- lead soic _n s - suffix (r -8) op282gsz - reel7 ? 40 c to +85 c 8- lead soic _n s - suffix (r -8) op482acbz -rl ? 40 c to +85 c 14- ball wlcsp cb -14-2 a2j op482acbz -r7 ? 40 c to +85 c 14- ball w l csp cb -14-2 a2j op 482gpz ? 40 c to +85 c 14- lead pdip p - suffix (n -14) op482gs ? 40 c to +85 c 14- lead soic_n s - suffix (r - 14) op482gs - reel ? 40 c to +85 c 14- lead soic_n s - suffix (r - 14) op482gs - reel7 ? 40 c to +85 c 14- lead soic_n s - suffix (r - 14) op482gsz ? 40 c to +85 c 14- lead soic_n s - suffix (r - 14) op482gsz - reel ? 40 c to +85 c 14- lead soic_n s - suffix (r - 14) op482gsz - reel7 ? 40 c to +85 c 14 - lead soic_n s - suffix (r - 14) 1 z = rohs compliant part. ? 1991 C 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d00301 - 0- 9/13(i)

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